1. Field of Invention
The present invention relates to the field of gallium nitride (GaN) devices and integrated circuits. In particular, the invention relates to a structure and method for isolating electrical devices in an integrated semiconductor device.
2. Description of the Related Art
Gallium nitride (GaN) semiconductor devices are increasingly desirable because of their ability to switch at high frequency, to carry large current, and to support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET). These types of devices can typically withstand high voltages, e.g., 30V-to-2000 Volts, while operating at high frequencies, e.g., 100 kHZ-100 GHz.
A GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer causes the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
The nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because the 2DEG region exists under the gate at zero gate bias, most nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted (i.e., removed) below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide and because they are easier to control with simple, low cost drive circuits. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
Integrated circuits (ICs) consist of devices that are located adjacent to each other. Such devices could interfere with each other if not electrically isolated, preventing the ICs from functioning properly.
FIGS. 1(a) and 1(b) illustrate an example of a conventional integrated circuit with two devices 10 and 20 with isolation area 30a, 30b disposed therebetween. Isolation area 30a, 30b is provided to intentionally remove the 2DEG to minimize parasitic capacitance. As shown, device 10 includes drain 11, gate 12 and source 13. Likewise, device 20 includes drain 21, gate 22 and source 23. The isolation area 30a, 30b electrically separates device 10 and device 20, so that the source 13 of device 10 and the source 23 of device 20 will be at different potentials.
For conventional fabricating methods, the isolation area 30a, 30b is formed by either removing the conductive layers by etching as illustrated in FIG. 1(a) or by converting the conductive layers into insulating layers by ion-implantation as illustrated FIG. 1(b). As further shown, the isolation area 30a, 30b is separated by a space of LISO. In gallium nitride (GaN) based materials, the isolation breakdown voltage may be proportional to LISO with 50˜200V per μm.
Isolation structures are typically fabricated with a dedicated mask as illustrated in FIGS. 2(a) and (b). In FIG. 2(a), isolation etching to create an isolation area 50c typically uses C12-based, BC13-based, or argon-based plasma. In FIG. 2(b), isolation implant species 50 are typically iron (Fe), magnesium (Mg), oxygen (O) or nitrogen (N). In fabricating an isolation area 50c, 50d with etching or ion-implantation, a dedicated isolation mask is used to form a patterned photoresist 40 on top of the wafer. The isolation area 50c, 50d is exposed while device regions of device 10 and device 20 are covered with the photoresist 40.
The existing methods of fabricating an isolation structure suffers from a number of disadvantages, including: (1) requiring a dedicated mask with the associated process steps that increase cost; (2) isolation by etching, which can result in an etched surface with high leakage current; and (3) isolation by ion-implantation in which the resistivity of the isolation region can degrade after the high temperature process.
Accordingly, it would be desirable to provide a process for fabricating an isolation structure that does not require a dedicated mask, results in a structure with reduced leakage current, and does not suffer from resistivity degradation of the isolation region.